The background description provided here is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
A pipeline analog-to-digital-converter (ADC) includes multiple stages. An analog input is first sampled and held steady by a sample-and-hold (S&H) circuit while a flash ADC in a first stage (Stage 1) quantizes it to N bits. The N-bit output is then fed to an N-bit DAC, and an analog output of the N-bit DAC is subtracted from the analog input to generate a residue. The residue is amplified and fed to a next stage (Stage 2). The amplified residue continues through the pipeline, providing N bits per stage until it reaches an M-bit flash ADC in the last stage, which resolves the last M LSB bits. Because the bits from each stage are determined at different points in time, all the bits corresponding to the same sample are time-aligned with shift registers before being fed to a digital error-correction logic. When a stage finishes processing a sample, determining the bits, and passing the residue to the next stage, the stage can then start processing the next sample received from the sample-and-hold embedded within each stage. This pipelining action provides high throughput.